#27 Depletion MOSFET self-bias — grounded gate is not zero V_GS

Below are all the lines written in the notebook together with the full narration transcript.

1. 1. The goal: understand what a grounded gate really sets

   Whole circuit: gate and source have different paths to ground

   Grounded gate does not imply V_GS=0

   Find Q, then check the assumed saturation model

   Narration transcript

   Look at the whole circuit first. The gate reaches ground through a large resistor, but the source reaches ground through a different resistor carrying the transistor current. Does a grounded gate mean zero gate-source voltage and a current equal to I D S S? Not necessarily. Our goal is to find the actual no-signal operating point. We will calculate current and terminal voltages, then check whether the saturation model we used is self-consistent.

2. 2. The goal: understand what a grounded gate really sets

   $\displaystyle V_{\mathrm{DD}}=20 V; R_{D}=6.2 k\Omega ; R_{S}=2.4 k\Omega$

   R_G=1 MΩ connects gate to ground

   Depletion MOSFET: I_DSS=8 [mA]; V_P=−8 V; body tied to source

   Narration transcript

   Preserve the original lesson forty-two values. The supply is twenty volts, the drain resistor six point two kilohms, and the source resistor two point four kilohms. The gate resistor is one megohm and connects to ground, not to the positive supply. The n-channel depletion MOSFET has I D S S equal to eight milliamps and V P equal to negative eight volts. Its body is tied to the source in the symbol. These connections define a self-bias circuit.

3. 3. The source resistor creates the control voltage

   $\displaystyle I_{G}\approx 0 \to V_{G}\approx 0$

   V_S=I_D R_S, generally nonzero

   V_GS=−I_D R_S; no negative supply needed

   Narration transcript

   In the ideal model, gate leakage is negligible. Therefore the voltage drop across the one-megohm gate resistor is approximately zero, and the gate is at ground potential. The source resistor carries the drain current, so its voltage is not generally zero. Source voltage equals drain current times source resistance. Subtract source voltage from gate voltage: V G S equals negative I D R S. The resistor in the source branch creates a negative control voltage without a separate negative gate supply.

4. 4. The source resistor creates the control voltage

   $\displaystyle x=\frac{I_{D}}{1 \left[\mathrm{mA}\right]}; V_{S}=2.4x V; V_{\mathrm{GS}}=-2.4x V$

   I_D rises → source rises → V_GS more negative

   Negative feedback, not an ideal current source

   Narration transcript

   Let x be the numerical drain current in milliamps. Multiplying milliamps by kilohms gives volts, so source voltage is two point four x volts and gate-source voltage is negative two point four x volts. This is the circuit relation, valid before we know the numerical current. If current tries to rise, the source rises and V G S becomes more negative, opposing that rise. This feedback helps stabilize the bias; it does not make an ideal constant-current source.

5. 5. Combine the circuit relation with the device model

   $\displaystyle I_{D}=8 \left[\mathrm{mA}\right] \left[1+\frac{V_{\mathrm{GS}}}{8 V}\right]^{2}$

   Substitute V_GS=−2.4x V

   $\displaystyle x=8\left(1-0.3x\right)^{2}$

   Narration transcript

   Use the ideal square-law saturation model: I D equals I D S S times the square of one minus V G S divided by V P. Since V P is negative eight volts, the expression becomes one plus V G S divided by eight volts. Substitute negative two point four x for V G S. Dividing two point four by eight gives zero point three, leaving one minus zero point three x inside the square. The resulting equation contains only x.

6. 6. Combine the circuit relation with the device model

   $\displaystyle \left(1-0.3x\right)^{2}=1-0.6x+0.09x^{2}$

   x=8−4.8x+0.72x²; move x

   $\displaystyle 0.72x^{2}-5.8x+8=0$

   Narration transcript

   Expand the square as one minus zero point six x plus zero point zero nine x squared. Remember the factor of two in the cross term. Multiply by eight to obtain x equals eight minus four point eight x plus zero point seven two x squared. Move the x from the left to the right. The final polynomial is zero point seven two x squared minus five point eight x plus eight equals zero. The extra negative x is why the coefficient is five point eight rather than four point eight.

7. 7. Check both roots, not just their current magnitudes

   $\displaystyle \Delta =10.6; x=\frac{5.8\pm \surd 10.6}{1.44}$

   Candidates: I_D≈1.767 [mA] and 6.289 [mA]

   Both below I_DSS: still test each gate voltage

   Narration transcript

   The quadratic formula gives a discriminant of ten point six. The numerator is five point eight plus or minus the square root of ten point six, and the denominator is one point four four. The roots are approximately one point seven six seven and six point two eight nine milliamps. Both happen to be less than the eight-milliamp I D S S value. That does not make them both valid. We must check the gate-source voltage produced by each current in the actual circuit.

8. 8. Check both roots, not just their current magnitudes

   Large root → V_GS≈−15.093 V

   −15.093 V < −8 V: outside conducting domain

   Squaring hides the sign; I_D<I_DSS alone is insufficient

   Narration transcript

   For the larger root, multiply the unrounded current by negative two point four. The gate-source voltage would be approximately negative fifteen point zero nine three volts. This is below the negative-eight-volt cutoff boundary, so reject this candidate. The conducting square-law model is being continued outside its valid domain. Squaring masks the sign problem and creates a positive algebraic current. Notice why checking only that current is less than I D S S would have accepted a physically invalid solution.

9. 9. Check both roots, not just their current magnitudes

   Small root:

   $\displaystyle I_{D}\approx 1.76683 \left[\mathrm{mA}\right]; V_{\mathrm{GS}}\approx -4.240 V$

   Above cutoff; positive source, negative self-bias

   Gate domain passed; drain-voltage check remains

   Narration transcript

   For the smaller root, use the unrounded current of about one point seven six six eight three milliamps. The gate-source voltage is approximately negative four point two four zero volts. This lies above cutoff and below zero, as expected for this grounded-gate self-bias circuit. The corresponding source voltage is positive. We have a valid gate-domain candidate, but we still need the drain-source voltage before accepting the assumed saturation region. A correct current equation is only one part of a complete bias analysis.

10. 10. Calculate the node and terminal-pair voltages

    $\displaystyle V_{S}=I_{D} R_{S}\approx 4.240 V$

    $\displaystyle V_{D}=20-I_{D} R_{D}\approx 9.046 V$

    Source not grounded → V_DS=V_D−V_S

    Narration transcript

    Calculate the node voltages relative to ground. The source voltage is drain current times two point four kilohms, or approximately four point two four zero volts. The drain voltage is twenty volts minus the current times six point two kilohms, giving approximately nine point zero four six volts. The source is not ground, so the drain voltage alone is not the voltage across the transistor. To get the transistor's drain-source voltage, subtract the source voltage from the drain voltage.

11. 11. Calculate the node and terminal-pair voltages

    V_DS=20−8.6 I_D≈4.805 V (I_D in [mA])

    Rounded I_D=1.767 [mA] gives 4.804 V

    About 1 [mV] difference: round only at the end

    Narration transcript

    Use the full-precision current to find V D S. The two resistors in the drain-source loop sum to eight point six kilohms. Subtract their total drop from the twenty-volt supply to obtain approximately four point eight zero five volts. The handwritten source displays four point eight zero four volts because it first rounds current to one point seven six seven milliamps. That roughly one-millivolt difference is a rounding effect, not a change in the circuit. Retain digits internally and round at the end.

12. 12. Verify saturation and close the voltage loop

    Saturation boundary:

    $\displaystyle V_{\mathrm{GS}}-V_{P}\approx 3.760 V$

    4.805 V > 3.760 V: saturation check passes

    Accept within ideal model; device ratings assumed adequate

    Narration transcript

    Check the condition required by the model. The saturation boundary is V G S minus V P. Negative four point two four zero minus negative eight gives approximately three point seven six zero volts. The available drain-source voltage is about four point eight zero five volts, so the candidate passes the saturation condition. Along with the earlier gate-domain check, this makes the operating point consistent with our ideal model. As always, we assume suitable real-device breakdown and power ratings; the square-law calculation does not supply those limits.

13. 13. Verify saturation and close the voltage loop

    

    Unrounded resistor + channel drops sum to 20 V

    Displayed sum 19.999 V: rounding

    Substitution returns the same I_D

    Narration transcript

    Now verify the complete voltage loop. The drain-resistor drop, transistor voltage, and source-resistor drop add to the twenty-volt supply when unrounded values are used. The displayed three-decimal values add to nineteen point nine nine nine volts, again just rounding. Substitute the unrounded V G S into the device equation and it returns the same drain current. These two checks confirm that the circuit and the transistor model agree, rather than merely confirming that a calculator can solve a quadratic.

14. 14. A self-consistent operating point, not a guessed current

    Self-bias line I_D=−V_GS/R_S meets device curve

    Q: I_D≈1.767 [mA]; V_GS≈−4.240 V; region checked

    Answer: V_G=0 does not mean V_GS=0

    Narration transcript

    On the graph, the purple line is the self-bias circuit relation, current equals negative gate-source voltage divided by source resistance. The blue curve is the device's saturation transfer characteristic. Their intersection gives approximately one point seven six seven milliamps and negative four point two four zero volts. The separate drain-source calculation then verified the region assumption. The gate being at zero volts did not make V G S zero: the source resistor supplied the missing part of the voltage reference.

15. 15. A self-consistent operating point, not a guessed current

    Read connections and voltage references first

    Test every root and verify saturation

    Positive V_GS is possible in general, not in this grounded-gate self-bias example

    Narration transcript

    Keep four habits. Read where each resistor is connected before applying a formula. Distinguish gate-to-ground voltage from gate-source voltage. Check every algebraic root against the actual model domain, even if its current looks reasonable. Finally, compute the transistor voltage and verify saturation. A depletion MOSFET permits positive gate-source voltage in general, but this particular grounded-gate circuit produces negative self-bias. The accepted result comes from the circuit connections and the device law agreeing at one operating point.

Source video: Electronics Basics #27 | Depletion MOSFET Self-Bias: Full DC Analysis (9:30)