#32 BJT emitter–JFET drain connection: use β+1 and preserve precision

Below are all the lines written in the notebook together with the full narration transcript.

1. 1. Locate the requested drain voltage

   Target V_D to ground; JFET drain = BJT emitter

   Grounded gate; lower transistor sets current, upper base loop gives voltage

   Narration transcript

   Look at the whole circuit and the red drain node. That is the voltage we want, measured relative to ground. The BJT sits above the JFET, so this time the JFET drain is also the BJT emitter. The gate is connected directly to ground. We will first find the current using the lower transistor, then use the upper transistor and its base resistor to recover the requested voltage.

2. 2. Locate the requested drain voltage

   $\displaystyle 16 V; R_{C}=3.6 k\Omega ; R_{B}=470 k\Omega ; R_{S}=2.4 k\Omega ; \beta =80$

   I_D=I_E=(β+1)I_B, not I_C

   Narration transcript

   Keep the original values: sixteen volts, a three point six kilohm collector resistor, a four hundred and seventy kilohm base resistor, and a two point four kilohm source resistor. BJT current gain is eighty. Its emitter current enters the JFET drain. Therefore drain current equals emitter current, not collector current. The emitter current includes base current, so it equals beta plus one times base current.

3. 3. Let the grounded gate set the relation

   $\displaystyle V_{G}=0; V_{S}=I_{D} R_{S}; V_{\mathrm{GS}}=-I_{D} R_{S}$

   $\displaystyle x=\frac{I_{D}}{1 \left[\mathrm{mA}\right]}; V_{\mathrm{GS}}=-2.4x V$

   Narration transcript

   Because the gate is grounded, gate to source voltage is zero minus source voltage. The source resistor carries the JFET current. Its voltage is drain current times two point four kilohms. Combining those facts gives a negative gate to source voltage that becomes more negative as current increases. Define x as the drain current measured in milliamps; then gate to source voltage is negative two point four times x, in volts.

4. 4. Let the grounded gate set the relation

   I_DSS=8 [mA]; V_P=−4 V; saturation square law

   x=8(1−0.6x)²; preserve outer minus

   Narration transcript

   The JFET data are eight milliamps at zero gate bias and a cutoff voltage of negative four volts. In the assumed saturation region, use Shockley’s square law. Substituting negative two point four x for gate to source voltage leaves one minus zero point six x inside the bracket. Notice the two negative signs in the voltage ratio. Their cancellation does not turn the outer subtraction into addition.

5. 5. Solve the current and choose the physical root

   (1−0.6x)²=1−1.2x+0.36x²; multiply by 8, move x

   $\displaystyle 2.88x^{2}-10.6x+8=0$

   Narration transcript

   Expand the square carefully. One minus zero point six x, squared, gives one minus one point two x plus zero point three six x squared. Multiply every term by eight. Then move the x from the left side to the right. The resulting quadratic is two point eight eight x squared, minus ten point six x, plus eight, equal to zero. Losing the cross term would give a different, incorrect current.

6. 6. Solve the current and choose the physical root

   $\displaystyle \Delta =20.2$

   Candidates: I_D≈1.060 [mA] and 2.621 [mA]

   Test each V_GS against the physical JFET interval

   Narration transcript

   Apply the quadratic formula. The discriminant is twenty point two. Taking both signs of its square root gives two candidates: one point zero six zero milliamps and two point six two one milliamps. Keep both for now. We do not choose a root merely because it is smaller or because it looks convenient. Each candidate must produce a gate to source voltage inside the physical JFET interval.

7. 7. Solve the current and choose the physical root

   Large root → V_GS≈−6.289 V

   Below −4 V cutoff: reject algebraic continuation

   Narration transcript

   Test the larger current with the source resistor relation. It produces a gate to source voltage of about negative six point two eight nine volts. Reject this candidate. That voltage is below the negative four volt cutoff boundary. Squaring an expression below cutoff can give a positive number, but it cannot bring the ideal conducting channel back. The algebraic continuation is not a physical solution of our transistor model.

8. 8. Solve the current and choose the physical root

   Small root: V_GS≈−2.544 V within [−4 V,0]

   V_S≈+2.544 V; still need V_D to check saturation

   Narration transcript

   The smaller current gives a gate to source voltage of negative two point five four four volts. This lies between negative four volts and zero, so it is the physical candidate. Its source voltage is the opposite sign, positive two point five four four volts, because the gate is grounded. We now know the current and source voltage, but still need the drain voltage to check the saturation assumption.

9. 9. Use the emitter current to find the drain node

   $\displaystyle I_{B}=\frac{I_{D}}{\beta +1}=\frac{I_{D}}{81}$

   I_B≈13.086 [μA]; not I_D/80; retain precision

   Narration transcript

   Use the shared current identity now. Drain current is emitter current, which equals eighty one times base current. Divide the unrounded drain current by eighty one. The base current is thirteen point zero eight six microamps. Do not divide by eighty: that would treat the known current as collector current. Do not round to thirteen microamps yet, because the large base resistor will magnify that small rounding change.

10. 10. Use the emitter current to find the drain node

    $\displaystyle V_{D}=V_{B}-0.7 V=16 V-I_{B} R_{B}-0.7 V$

    V_D≈9.149 V to ground; not V_DS

    Narration transcript

    Follow the base loop from the sixteen volt supply. Subtract base current times four hundred and seventy kilohms to reach the base. Subtract the assumed zero point seven volt base to emitter drop to reach the shared emitter and drain node. Using the unrounded current, the requested drain voltage is nine point one four nine volts. This is a node voltage to ground, not the JFET drain to source voltage.

11. 11. Verify the regions and keep enough precision

    R_C matters for BJT forward-active feasibility

    $\displaystyle I_{C}=80 I_{B}\approx 1.047 \left[\mathrm{mA}\right]$

    V_C≈12.231 V > V_B; collector-base junction reverse biased

    Narration transcript

    The collector resistor did not appear in the base-loop calculation, but it is not irrelevant. It determines whether the BJT can support the assumed current in its forward active region. Collector current is eighty times base current, about one point zero four seven milliamps. Subtract its resistor drop from sixteen volts. The collector voltage is twelve point two three one volts, above the base voltage. That supports the assumed reverse biased collector to base junction.

12. 12. Verify the regions and keep enough precision

    JFET voltage:

    $\displaystyle V_{\mathrm{DS}}\approx 6.605 V$

    Required boundary:

    $\displaystyle V_{\mathrm{GS}}-V_{P}\approx 1.456 V$

    6.605 V > 1.456 V; both device-region checks pass

    Narration transcript

    Check the JFET separately. Drain to source voltage is the drain node minus the source node, about six point six zero five volts. The saturation boundary is gate to source voltage minus pinch off voltage, about one point four five six volts. The available voltage is larger, so saturation is consistent. Together with the BJT check, this confirms a self-consistent operating point within our stated ideal device models.

13. 13. Verify the regions and keep enough precision

    

    13.086 [μA] → about 9.15 V; 13 [μA] → 9.19 V

    Small ΔI_B through 470 kΩ causes about 41 [mV] difference

    Narration transcript

    Why do the original source versions show slightly different final numbers? One retains about thirteen point zero eight six microamps and reports nine point one five volts. The shorter version rounds base current to thirteen microamps and obtains nine point one nine volts. These describe the same circuit. A difference of only about zero point zero eight six microamps creates roughly forty one millivolts across four hundred and seventy kilohms. Keep guard digits until the final answer.

14. 14. Read the operating point from both models

    

    JFET curve and self-bias line set physical I_D and V_GS

    Shared emitter current → I_B → V_D; then check both devices

    Narration transcript

    The transfer graph connects the lower circuit to the device. The blue curve is the JFET law only in its physical gate voltage interval. The purple line is the source resistor relation. Their intersection gives the valid current and gate to source voltage. We then used that emitter current to calculate base current and the drain node. The graph identifies a candidate; the voltage checks establish that both transistors can operate as assumed.

15. 15. Read the operating point from both models

    Read shared terminals, reject invalid roots, keep guard digits

    Ideal gate, fixed V_BE and simplified laws; educational DC model

    Narration transcript

    Keep three habits from this example. Read which terminals share a node before equating currents. Reject roots outside the device model instead of trusting algebra alone. And preserve enough precision when a small current flows through a large resistor. We assumed negligible gate current, a fixed base to emitter drop, and ideal saturation laws. The result is a checked educational DC model, not an exact prediction for every physical device.

Source video: Electronics Basics #32 | BJT + JFET Bias: Follow the Emitter Current (7:55)