#39 MOSFET common source: gate control and finite output resistance

Below are all the lines written in the notebook together with the full narration transcript.

1. 1. A voltage-controlled change

   

   Raise the gate by 1 [mV]; ideal gate current is zero. Does the drain respond?

   Gate controls drain-current change; R_D converts it to an inverted voltage

   Narration transcript

   Imagine raising a MOSFET gate voltage by just one millivolt. In our ideal midband model, no signal current enters the gate. Does that mean nothing can happen at the drain? Watch the gate signal and the drain voltage together. The gate controls a change in drain current without receiving that current itself. The drain resistor converts the change into an output voltage. We will explain why the output falls, and why the transistor's finite output resistance makes the gain smaller than the simplest estimate.

2. 2. A voltage-controlled change

   

   Grounded source; gate input, drain output; constant supply becomes AC ground

   Coupling capacitors short only in the stated band; keep saturation bias separate

   Narration transcript

   The source is grounded. The input is applied to the gate and the output is taken from the drain. R D connects the drain to the DC supply. For the small-signal circuit, a constant supply becomes AC ground. The coupling capacitors are approximated as shorts only in the frequency range we are studying. An established bias arrangement keeps the MOSFET in saturation; the simplified AC drawing does not design that arrangement. Keep the settled bias separate from the tiny changes drawn on the instruments.

3. 3. A voltage-controlled change

   Controlled source g_m v_gs and r_o connect drain to source; r_o is a local slope

   R_D ∥ r_o at the output; all branches obey the same current balance

   Narration transcript

   Replace the MOSFET by a controlled current source from drain to source, with value g m times v g s, and a resistance r o between the same two terminals. R o represents the local slope of the drain-current versus drain-voltage characteristic. It is not a resistor at the gate and not the external drain resistor. Since the source and supply are both AC ground, r o and R D appear in parallel at the output. The controlled source and both passive paths must satisfy the same current balance.

4. 4. Find the input and output resistances

   

   Ideal insulated gate, no capacitance: i_g=0 → intrinsic R_in→∞

   Real bias resistors, capacitance and leakage limit impedance; ideal open gate has no divider loss

   Narration transcript

   Input resistance is the input voltage divided by the input current. With an insulated ideal gate and capacitances neglected, the gate current is zero. Therefore the intrinsic input resistance is infinite. This is a model statement, not a claim that every real amplifier input has infinite impedance. Gate-bias resistors provide additional input paths, and gate capacitance draws changing current at higher frequencies. A series source resistance causes no divider loss against the ideal open gate, but it can matter once those omitted paths are included.

5. 5. Find the input and output resistances

   Zero input signal but retain DC bias; v_gs=0; drain test sees R_D ∥ r_o

   R_out=R_D ∥ r_o; as r_o→∞, R_out→R_D; external load is separate

   Narration transcript

   To find output resistance, set the independent input signal to zero while retaining the DC bias that establishes g m. Now v g s is zero, so the controlled current source becomes zero. Apply a test voltage at the drain. Its current flows through R D and r o in parallel. Therefore output resistance is R D parallel r o. Output resistance is a port property; it is not the same thing as a later external load. If r o tends to infinity, this result approaches R D.

6. 6. Derive gain and transconductance

   $\displaystyle v_{o}\left(\frac{1}{R_{D}}+\frac{1}{r_{o}}\right)+g_{m} v_{\mathrm{gs}}=0$

   Grounded source: v_gs=v_in; A_v=−g_m(R_D ∥ r_o); gate↑ → drain↓

   Narration transcript

   Return to the current balance at the drain. The output voltage multiplied by the sum of the two conductances must cancel g m times v g s. Solving gives output voltage equal to negative g m times v g s times R D parallel r o. The grounded source makes v g s equal to the input voltage. Divide by that input and obtain voltage gain: negative g m times R D parallel r o. The negative sign means a positive gate change produces a negative drain change around the bias point.

7. 7. Derive gain and transconductance

   

   Ideal long-channel square law: k=μC_ox(W/L); I_D=kV_OV²/2

   g_m=kV_OV=√(2kI_D)

   V_GS=V_TH+√(2I_D/k); ideal g_m estimate is not a complete finite-r_o model

   Narration transcript

   Where can g m come from? In the ideal long-channel saturation square law, define k as mobility times oxide capacitance per area times the width-to-length ratio. Drain current is one half k times overdrive voltage squared. Differentiating with respect to gate-source voltage gives g m equal to k times overdrive. Equivalently, g m is the square root of two k I D. Rearranging the same current law gives V G S equal to threshold plus the square root of two I D divided by k. These ideal relations estimate g m; they are not a complete model of finite output resistance.

8. 8. Check one consistent operating point

   I_DQ=1 [mA]; g_m=2 mS; R_D=4.7 kΩ; r_o=50 kΩ; V_D=7.3 V>V_OV=1 V

   Supplemental values; ideal square-law illustration:

   $\displaystyle k=2 \left[\mathrm{mA}\right]/V², V_{\mathrm{TH}}=1 V \to V_{\mathrm{GS}}=2 V$

   Narration transcript

   Use a supplemental example with drain bias current one milliamp, g m two millisiemens, R D four point seven kilohms, r o fifty kilohms and a twelve volt supply. A one volt overdrive leaves the drain at seven point three volts, comfortably above the saturation boundary in this simplified model. The original Turkish source provides no numerical values; these are teaching choices. Separately, the ideal square law with k two milliamps per volt squared and threshold one volt gives one volt overdrive, two volts gate-source bias and the same two millisiemens g m.

9. 9. Check one consistent operating point

   

   $\displaystyle R_{D} ∥ r_{o}=\frac{4700\times 50000}{54700}\approx 4296.161 \Omega$

   $\displaystyle A_{v}\approx -8.592$

   $\displaystyle v_{\mathrm{in}}=+1 \left[\mathrm{mV}\right] \to v_{o}\approx -8.592 \left[\mathrm{mV}\right]; g_{m} v_{\mathrm{gs}}=+2 \left[\mathrm{μA}\right]$

   Δi_D=g_m v_gs+v_o/r_o≈1.828 [μA], not 2 [μA]

   Narration transcript

   Calculate the parallel resistance using four thousand seven hundred times fifty thousand, divided by their sum. The result is about four thousand two hundred ninety six point one six one ohms. Multiply by negative zero point zero zero two siemens. Voltage gain is about negative eight point five nine two volts per volt. A positive one millivolt input gives negative eight point five nine two millivolts output. The controlled-source increment is positive two microamps. The r o branch has a negative current increment, so the total transistor drain-current increment is about one point eight two eight microamps, not exactly two.

10. 10. Check one consistent operating point

    

    Same g_m and R_D, r_o→∞: A_v=−9.4; v_o=−9.4 [mV] for +1 [mV]

    Finite r_o reduces resistance and gain magnitude, not inversion; compare local models

    Narration transcript

    Now compare the same local g m and drain resistor while increasing r o toward infinity. The parallel resistance approaches four point seven kilohms. The idealized gain becomes negative nine point four volts per volt, and a one millivolt input produces negative nine point four millivolts. The finite resistance did not change the inversion. It reduced the effective output resistance and the magnitude of gain. We are comparing two local small-signal models with the same stated bias parameters, not physically changing a device parameter without consequences.

11. 11. State the limits and answer the question

    External AC-coupled R_L:

    $\displaystyle A_{\mathrm{loaded}}=-g_{m}\left(R_{D} ∥ r_{o} ∥ R_{L}\right)$

    Own R_out excludes external load; real gate-bias resistance also limits R_in

    Narration transcript

    If an external load is attached through an ideal midband coupling capacitor, it adds a third output path. Replace the two-resistance parallel combination by R D parallel r o parallel R L. The loaded voltage gain is negative g m times that combination. But the amplifier's own output resistance remains the port value found with the external load removed. At the input, an actual gate-bias resistance would similarly limit the input resistance. State what belongs to the amplifier and what has been attached to it before quoting a resistance or a gain.

12. 12. State the limits and answer the question

    

    Small signal around saturation only; large signal and frequency effects change the model

    Temperature/fabrication shift Q; check headroom and state all assumptions

    Narration transcript

    The model is linear only for small excursions around the chosen saturation bias. Large inputs can make g m vary significantly or drive the device out of saturation. Real gates have capacitance and leakage, and coupling capacitors cannot be short circuits at every frequency. Temperature and fabrication also change the operating point. These instruments visualize a calculated local model, not a complete semiconductor simulation. The useful habit is to name the assumptions before applying a compact gain formula and to check that the predicted voltages remain inside the allowed operating region.

13. 13. State the limits and answer the question

    Answer: gate↑ → controlled drain current↑ → drain voltage↓, even with i_g=0

    Finite r_o adds an output path: −8.592 [mV] versus ideal −9.4 [mV] for +1 [mV] input

    Narration transcript

    Return to the opening question. Raise the gate while the source stays fixed. The controlled drain current rises, so the drain voltage falls. No signal current has to enter the ideal gate for this voltage control to occur. With finite r o, the output-current balance includes another path, reducing output resistance and gain magnitude. Our one millivolt gate change gives about negative eight point five nine two millivolts at the drain, compared with negative nine point four in the infinite r o limit. That is the mechanism behind negative g m times R D parallel r o.

Source video: Electronics Basics #39 | MOSFET Common Source: Why Does the Output Fall? (9:07)