Electronics Basics #19 | Two Stacked Transistors — Voltage-Divider Bias (β Drops Out)

Instructor: Dr. Süleyman Burak ÇELİK

We've solved the voltage-divider bias for a single transistor. Now we raise the stakes: two transistors stacked one on top of the other, sharing a single bias divider. It looks like twice the circuit — but it turns out to be one clean pass, if you read it the right way. The circuit: V_CC = 20 V, a three-resistor divider (7.5 kilo-ohms, 6.2 kilo-ohms, 3.9 kilo-ohms), a collector resistor of 1.5 kilo-ohms, an emitter resistor of 1 kilo-ohm, and two transistors with beta = 100. Find: the collector current and the collector-emitter voltage of each transistor — four numbers in all. The key picture: imagine one pipe with two water turbines stacked inside it. The same stream turns both — whatever flows through the top must flow through the bottom. That single shared current is what makes the whole problem simple. What you'll learn: - One divider, two taps: a three-resistor ladder hands you two base voltages at once (V_B1 = 4.43 V at the lower junction, V_B2 = 11.48 V at the upper) - One current path: the two transistors are chained, so the top collector current equals the bottom one — solve them together, from the bottom up - Why beta drops out again: in a stiff divider the base voltages come from the resistors and the current from a voltage and the emitter resistor, so the operating point never depends on beta - Two KVL loops finish the job: the middle loop gives the bottom transistor's V_CE, the outer loop gives the top one's Results: V_B1 = 4.43 V, V_B2 = 11.48 V, I_C1 = I_C2 = 3.73 mA, V_CE1 = 7.05 V, V_CE2 = 3.62 V. Sanity check: the four voltage drops around the outer loop add right back up to the 20-volt supply. Chapters: 0:00 Intro 0:03 Two transistors, one divider — the setup and the turbine picture 1:10 Read the circuit first: three observations 2:42 Step 1 — two base voltages from one ladder 4:14 Step 2 — one current for both transistors (beta drops out) 5:40 Step 3 — the bottom transistor's V_CE (middle loop) 6:53 Step 4 — the top transistor's V_CE (outer loop) 8:12 The whole stack, summarized + what comes next Next lesson: graphical DC analysis — the load line and the Q-point, where the transistor's curves meet the circuit's straight line. Reference: Boylestad, Electronic Devices and Circuit Theory