Electronics Basics #25 | JFET Divider Bias — Positive Gate, Negative VGS

Instructor: Dr. Süleyman Burak ÇELİK

A positive gate potential need not mean positive gate-source voltage. Solve the original16 V divider-bias circuit with upper2.1 MΩ and lower270 kΩ resistors, RD=2.4 kΩ and RS=1.5 kΩ. Find the unloaded divider voltage, derive both current roots, and distinguish VD, VDS and VDG. Ideal result: ID≈2.416 mA, VG≈1.823 V, VGS≈−1.802 V, VDS≈6.576 V. Ideal DC model: gate leakage neglected, saturation checked, adequate device ratings assumed. Internal calculations retain unrounded values. Real components have parameter tolerances. Chapters: 0:00 The goal: a positive gate can still give negative bias 1:02 Use the unloaded divider to find the gate voltage 2:46 Combine the divider, source resistor and device 5:10 Solve both roots and select the physical candidate 6:18 Keep each voltage reference explicit 8:08 Verify the operating region and the circuit 9:26 The complete, checked operating point