Electronics Basics #31 | JFET + BJT Bias: Approximation vs Finite Beta

Instructor: Dr. Süleyman Burak ÇELİK

Find the drain and collector voltages in the original combined JFET/BJT bias circuit. Start with the whole circuit, solve the original unloaded-divider approximation, then include finite base current and compare the two stated models. Original lesson 46: 16 V supply, RD 2.7 kΩ, RE 1.6 kΩ, 82 kΩ / 24 kΩ base divider, and 1 MΩ between base and JFET gate. IDSS = 12 mA, VP = −6 V, beta = 180 and assumed VBE = 0.7 V. The two original PDF versions describe the same problem. Approximation: ID ≈ 1.827 mA, VC ≈ 7.282 V, VD ≈ 11.068 V (11.067 V with the original early current rounding). Finite-beta model: ID ≈ 1.707 mA, VC ≈ 7.184 V, VD ≈ 11.391 V. We verify KCL, voltage loops, JFET saturation and BJT forward-active operation. ID = IC, but IE = IC + IB. The refined calculation is still an idealized DC model: negligible gate current, fixed VBE, no Early effect and a simplified Shockley law. It is not an exact prediction for a real transistor. Chapters: 0:00 Start with the two voltages we want 1:03 First pass: the original approximation 2:04 Connect the JFET law to the node voltages 5:35 Include the base current and divider loading 8:28 Check both transistors, then compare