Electronics Basics #33 | Common Emitter: Why Does the Output Invert?

Instructor: Dr. Süleyman Burak ÇELİK

Why does a rising base signal produce a falling collector signal? Start with the whole common-emitter stage, watch model-driven 3D instruments, then derive input resistance, output resistance and signed voltage gain from the hybrid-pi model. Based on original lesson 48. We separate the DC operating point from the incremental signal, explain midband assumptions, and derive gm = IC/VT, rπ = β/gm, Rin = rπ and Rout = RC ∥ ro for the stated simplified circuit. Collector-node current balance gives Av = −gm(RC ∥ ro). The clearly labelled teaching example adds IC = 1 mA, β = 100, VT = 26 mV, RC = 2 kΩ and ro = 100 kΩ: gm ≈ 38.46 mS, rπ = 2.6 kΩ and unloaded gain ≈ −75.41 V/V. With RL = 10 kΩ and Rs = 1 kΩ, stage gain ≈ −63.05 and source-to-output gain ≈ −45.54. These numerical values extend the symbolic source note. The base-bias network is omitted from the signal topology; a valid forward-active operating point is assumed. This is not a complete buildable circuit. The 3D markers use separate normalized scales and show changes around bias, not moving electrons, total currents or a physical low-frequency test. Finite output resistance, loading, small-signal limits and cutoff/saturation headroom remain explicit. Chapters: 0:00 See the input and output first 1:22 Separate the signal from the operating point 2:40 Replace the transistor with its local model 4:43 Read the input and output resistances 6:03 Derive the sign and size of the gain 9:03 Apply the model without losing its limits